Optimization on fixed low latency implementation of the GBT core in FPGA

Chen, K.; Chen, H.; Wu, W.; Xu, H.; Yao, L.

doi:10.1088/1748-0221/12/07/P07011

Optimization on fixed low latency implementation of the GBT core in FPGA

Journal Article · Tue Jul 11 00:00:00 EDT 2017 · Journal of Instrumentation

DOI:https://doi.org/10.1088/1748-0221/12/07/P07011· OSTI ID:1424952

Chen, K. ^[1]; Chen, H. ^[1]; Wu, W. ^[1]; Xu, H. ^[1]; Yao, L. ^[1]

Brookhaven National Lab. (BNL), Upton, NY (United States)

We present that in the upgrade of ATLAS experiment, the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system is used to interface the front end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. Finally, the system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

Research Organization:: Brookhaven National Laboratory (BNL), Upton, NY (United States)

Sponsoring Organization:: USDOE Office of Science (SC), High Energy Physics (HEP) (SC-25)

Grant/Contract Number:: SC0012704

OSTI ID:: 1424952

Alternate ID(s):: OSTI ID: 22656283

Report Number(s):: BNL-200039-2018-JAAM

Journal Information:: Journal of Instrumentation, Journal Name: Journal of Instrumentation Journal Issue: 07 Vol. 12; ISSN 1748-0221

Publisher:: Institute of Physics (IOP)Copyright Statement

Country of Publication:: United States

Language:: English

References (8)

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FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework Anderson, J.; Bauer, K.; Borga, A. Journal of Instrumentation, Vol. 11, Issue 12 https://doi.org/10.1088/1748-0221/11/12/C12023	journal	December 2016
Optimizing latency in Xilinx FPGA implementations of the GBT Muschter, S.; Baron, S.; Bohm, C. Journal of Instrumentation, Vol. 5, Issue 12 https://doi.org/10.1088/1748-0221/5/12/C12017	journal	December 2010
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Development and application of a modular test system for the HV-CMOS pixel sensor R&D of the ATLAS HL-LHC upgrade Liu, H.; Benoit, M.; Chen, H. Radiation Detection Technology and Methods, Vol. 3, Issue 3 https://doi.org/10.1007/s41605-019-0126-y	journal	June 2019

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