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Title: Optimization on fixed low latency implementation of the GBT core in FPGA

Journal Article · · Journal of Instrumentation
 [1];  [1];  [1];  [1];  [1]
  1. Brookhaven National Lab. (BNL), Upton, NY (United States)
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We present that in the upgrade of ATLAS experiment, the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system is used to interface the front end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. Finally, the system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

Research Organization:
Brookhaven National Lab. (BNL), Upton, NY (United States)
Sponsoring Organization:
USDOE Office of Science (SC), High Energy Physics (HEP)
Grant/Contract Number:
SC0012704
OSTI ID:
1424952
Report Number(s):
BNL-200039-2018-JAAM; TRN: US1801975
Journal Information:
Journal of Instrumentation, Vol. 12, Issue 07; ISSN 1748-0221
Publisher:
Institute of Physics (IOP)Copyright Statement
Country of Publication:
United States
Language:
English
Citation Metrics:
Cited by: 8 works
Citation information provided by
Web of Science

References (7)

The GBT-FPGA core: features and challenges journal March 2015
FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades journal December 2015
Optimizing latency in Xilinx FPGA implementations of the GBT journal December 2010
TTC distribution for LHC detectors journal June 1998
Fixed-Latency, Multi-Gigabit Serial Links With Xilinx FPGAs journal February 2011
High-speed, fixed-latency serial links with Xilinx FPGAs journal February 2014
The development of the global feature extractor for the LHC Run-3 upgrade of the L1 calorimeter trigger system conference June 2016

Cited By (1)

Development and application of a modular test system for the HV-CMOS pixel sensor R&D of the ATLAS HL-LHC upgrade journal June 2019

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Related Subjects

47 OTHER INSTRUMENTATION
Fixed low latency transmission
GBT link
Transceiver in FPGA