Design of a low parasitic inductance SiC power module with double-sided cooling

Conference · Wed Mar 01 04:00:00 EST 2017

DOI:https://doi.org/10.1109/APEC.2017.7931132· OSTI ID:1399433

Yang, Fei ^[1]; Liang, Zhenxian ^[2]; Wang, Fei ^[3]; Wang, Zhiqiang ^[3]

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1. The University of Tennessee, Knoxville
2. Cree Inc.
3. ORNL

In this paper, a low-parasitic inductance SiC power module with double-sided cooling is designed and compared with a baseline double-sided cooled module. With the unique 3D layout utilizing vertical interconnection, the power loop inductance is effectively reduced without sacrificing the thermal performance. Both simulations and experiments are carried out to validate the design. Q3D simulation results show a power loop inductance of 1.63 nH, verified by the experiment, indicating more than 60% reduction of power loop inductance compared with the baseline module. With 0Ω external gate resistance turn-off at 600V, the voltage overshoot is less than 9% of the bus voltage at a load of 44.6A.

• Research Organization: Oak Ridge National Laboratory (ORNL), Oak Ridge, TN (United States)
• Sponsoring Organization: USDOE Office of Energy Efficiency and Renewable Energy (EERE), Vehicle Technologies Office (EE-3V)
• DOE Contract Number: AC05-00OR22725
• OSTI ID: 1399433
• Country of Publication: United States
• Language: English