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Title: Lateral electrochemical etching of III-nitride materials for microfabrication

Abstract

Conductivity-selective lateral etching of III-nitride materials is described. Methods and structures for making vertical cavity surface emitting lasers with distributed Bragg reflectors via electrochemical etching are described. Layer-selective, lateral electrochemical etching of multi-layer stacks is employed to form semiconductor/air DBR structures adjacent active multiple quantum well regions of the lasers. The electrochemical etching techniques are suitable for high-volume production of lasers and other III-nitride devices, such as lasers, HEMT transistors, power transistors, MEMs structures, and LEDs.

Inventors:
Publication Date:
Research Org.:
Yale Univ., New Haven, CT (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1345219
Patent Number(s):
9,583,353
Application Number:
13/923,248
Assignee:
Yale University CHO
DOE Contract Number:
FG02-07ER46387
Resource Type:
Patent
Resource Relation:
Patent File Date: 2013 Jun 20
Country of Publication:
United States
Language:
English
Subject:
36 MATERIALS SCIENCE; 37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CHEMISTRY

Citation Formats

Han, Jung. Lateral electrochemical etching of III-nitride materials for microfabrication. United States: N. p., 2017. Web.
Han, Jung. Lateral electrochemical etching of III-nitride materials for microfabrication. United States.
Han, Jung. Tue . "Lateral electrochemical etching of III-nitride materials for microfabrication". United States. doi:. https://www.osti.gov/servlets/purl/1345219.
@article{osti_1345219,
title = {Lateral electrochemical etching of III-nitride materials for microfabrication},
author = {Han, Jung},
abstractNote = {Conductivity-selective lateral etching of III-nitride materials is described. Methods and structures for making vertical cavity surface emitting lasers with distributed Bragg reflectors via electrochemical etching are described. Layer-selective, lateral electrochemical etching of multi-layer stacks is employed to form semiconductor/air DBR structures adjacent active multiple quantum well regions of the lasers. The electrochemical etching techniques are suitable for high-volume production of lasers and other III-nitride devices, such as lasers, HEMT transistors, power transistors, MEMs structures, and LEDs.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Feb 28 00:00:00 EST 2017},
month = {Tue Feb 28 00:00:00 EST 2017}
}

Patent:

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  • A method for impurity-induced disordering in III-nitride materials comprises growing a III-nitride heterostructure at a growth temperature and doping the heterostructure layers with a dopant during or after the growth of the heterostructure and post-growth annealing of the heterostructure. The post-growth annealing temperature can be sufficiently high to induce disorder of the heterostructure layer interfaces.
  • The III-V nitride compound semiconductors are attracting considerable attention for blue and ultraviolet light emitting diodes (LEDs) and lasers as well as high temperature electronics due to their wide band gaps and high dielectric constants. The recent progress observed in the growth of these materials has not been matched by progress in processing techniques to fabricate more highly sophisticated devices. Patterning these materials has been especially difficult due to the relatively inert chemical nature of the group-III nitrides. The authors review dry etch techniques which have been used to pattern these materials including electron cyclotron resonance (ECR), reactive ion etchmore » (RIE), and chemically assisted ion beam etching (CAIBE). ECR etch rates greater than 3,800 {angstrom}/min for InN, 3,500 {angstrom}/min for GaN, and 1,170 A/min for AlN are reported. Etch anisotropy, surface morphology, and near-surface stoichiometry will be discussed.« less
  • Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfermore » process may be performed at temperatures of 50 C or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense. 57 figs.« less
  • Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfermore » process may be performed at temperatures of 50.degree. C. or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense.« less
  • Methods for facilitating fabricating semiconductor structures are provided which include: providing a multilayer structure including a semiconductor layer, the semiconductor layer including a dopant and having an increased conductivity; selectively increasing, using electrochemical processing, porosity of the semiconductor layer, at least in part, the selectively increasing porosity utilizing the increased conductivity of the semiconductor layer; and removing, at least in part, the semiconductor layer with the selectively increased porosity from the multilayer structure. By way of example, the selectively increasing porosity may include selectively, anodically oxidizing, at least in part, the semiconductor layer of the multilayer structure.