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Title: High voltage semiconductor devices and methods of making the devices

Abstract

A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.

Inventors:
; ;
Publication Date:
Research Org.:
MONOLITH SEMICONDUCTOR INC. Round Rock, TX (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1345218
Patent Number(s):
9,583,482
Application Number:
14/619,742
Assignee:
MONOLITH SEMICONDUCTOR INC. ARPA-E
DOE Contract Number:
AR0000442
Resource Type:
Patent
Resource Relation:
Patent File Date: 2015 Feb 11
Country of Publication:
United States
Language:
English
Subject:
47 OTHER INSTRUMENTATION; 36 MATERIALS SCIENCE

Citation Formats

Matocha, Kevin, Chatty, Kiran, and Banerjee, Sujit. High voltage semiconductor devices and methods of making the devices. United States: N. p., 2017. Web.
Matocha, Kevin, Chatty, Kiran, & Banerjee, Sujit. High voltage semiconductor devices and methods of making the devices. United States.
Matocha, Kevin, Chatty, Kiran, and Banerjee, Sujit. Tue . "High voltage semiconductor devices and methods of making the devices". United States. doi:. https://www.osti.gov/servlets/purl/1345218.
@article{osti_1345218,
title = {High voltage semiconductor devices and methods of making the devices},
author = {Matocha, Kevin and Chatty, Kiran and Banerjee, Sujit},
abstractNote = {A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Feb 28 00:00:00 EST 2017},
month = {Tue Feb 28 00:00:00 EST 2017}
}

Patent:

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  • A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias.more » The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.« less
  • A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+more » region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.« less
  • A solar cell which has high efficiency and which can be fabricated at low cost is described. The cell includes a semiconductor wafer with a front radiation-receiving surface which is entirely open and free of current conducting grids and also includes an array of interconnection paths which carry photocurrent from the front surface through the cell to metal electrodes on the rear surface of the cell.
  • A semiconductor device having at least one P-N junction and a multiple-zone junction termination extension (JTE) region which uniformly merges with the reverse blocking junction is disclosed. The blocking junction is graded into multiple zones of lower concentration dopant adjacent termination to facilitate merging of the JTE to the blocking junction and placing of the JTE at or near the high field point of the blocking junction. Preferably, the JTE region substantially overlaps the graded blocking junction region. A novel device fabrication method is also provided which eliminates the prior art step of separately diffusing the JTE region.
  • This patent describes improvement in the process of fabricating a semiconductor device including, when complete, at least one P-N junction, a first region of semiconductor material of one conductivity type having an upper surface and forming one side of the junction, a second region of semiconductor material having a lower surface and forming the other side of the junction, the second region being formed within the first region with conductivity type opposite that of the first region; and wherein the P-N junction includes a terminated portion at the upper surface of the first region, the second region includes a gradedmore » region adjacent to termination of the P-N junction, and the first region at a width W{sub D} when the junction is reverse-biased to its ideal breakdown voltage; the improvement comprises: forming a first mask of not so uniform thickness on the semiconductor device adjacent to the terminated portion to be used in forming a junction termination extension region; simultaneously doping the first and second portions of the first region through the first mask with the same concentration of dopant to form in the first region, a first zone contiguous with the terminated portion and a second zone adjacent the first zone; forming a second mask of not so uniform thickness on the semiconductor device adjacent the terminated portion and remote from the balance of the junction termination extension region, to be used in forming the second region including the graded region; simultaneously doping the first and second portions of the first region through the second mask with the same concentration of dopant to form in the first region the second region such that the second region has a first zone contiguous with the terminated portion and a second zone adjacent the first zone; and simultaneously diffusing the junction termination extension implant and the second region dopant implant.« less