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Title: Understanding EUV mask blank surface roughness induced LWR and associated roughness requirement

Journal Article · · Proceedings of SPIE - The International Society for Optical Engineering
DOI:https://doi.org/10.1117/12.2087041· OSTI ID:1229862
 [1];  [1];  [2];  [2];  [2]
  1. Intel Corp., Santa Clara, CA (United States)
  2. Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)

Extreme ultraviolet lithography (EUVL) mask multi-layer (ML) blank surface roughness specification historically comes from blank defect inspection tool requirement. Later, new concerns on ML surface roughness induced wafer pattern line width roughness (LWR) arise. In this paper, we have studied wafer level pattern LWR as a function of EUVL mask surface roughness via High-NA Actinic Reticle Review Tool. We found that the blank surface roughness induced LWR at current blank roughness level is in the order of 0.5nm 3σ for NA=0.42 at the best focus. At defocus of ±40nm, the corresponding LWR will be 0.2nm higher. Further reducing EUVL mask blank surface roughness will increase the blank cost with limited benefit in improving the pattern LWR, provided that the intrinsic resist LWR is in the order of 1nm and above.

Research Organization:
Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States). Materials Sciences Division
Sponsoring Organization:
USDOE
DOE Contract Number:
AC02-05CH11231
OSTI ID:
1229862
Report Number(s):
LBNL-175875; ir:175875
Journal Information:
Proceedings of SPIE - The International Society for Optical Engineering, Vol. 9422; ISSN 0277-786X
Publisher:
SPIE
Country of Publication:
United States
Language:
English

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