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Shared performance monitor in a multiprocessor system

Patent ·
OSTI ID:1176464
; ;
A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU comprises: a plurality of performance counters each for counting signals representing occurrences of events from one or more the plurality of processor units in the multiprocessor system; and, a plurality of input devices for receiving the event signals from one or more processor devices of the plurality of processor units, the plurality of input devices programmable to select event signals for receipt by one or more of the plurality of performance counters for counting, wherein the PMU is shared between multiple processing units, or within a group of processors in the multiprocessing system. The PMU is further programmed to monitor event signals issued from non-processor devices.
Research Organization:
International Business Machines Corporation, Armonk, NY (United States)
Sponsoring Organization:
USDOE
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Number(s):
8,230,433
Application Number:
11/768,777
OSTI ID:
1176464
Country of Publication:
United States
Language:
English

References (8)

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Performance evaluation of adaptive MPI
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  • Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '06 https://doi.org/10.1145/1122971.1122976
conference January 2006
Synchronization, coherence, and event ordering in multiprocessors journal February 1988
Blue Gene/L advanced diagnostics environment journal March 2005
Optimization of MPI collective communication on BlueGene/L systems conference January 2005
Intel 870: a building block for cost-effective, scalable servers journal March 2002
Directory-based cache coherence in large-scale multiprocessors journal June 1990
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures journal August 2005

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Related Subjects

97 MATHEMATICS AND COMPUTING