EqualChance: Addressing Intra-set Write Variation to Increase Lifetime of Non-volatile Caches

Conference · Wed Jan 01 04:00:00 EST 2014

OSTI ID:1159425

Mittal, Sparsh ^[1]; Vetter, Jeffrey S ^[1]

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1. ORNL

To address the limitations of SRAM such as high-leakage and low-density, researchers have explored use of non-volatile memory (NVM) devices, such as ReRAM (resistive RAM) and STT-RAM (spin transfer torque RAM) for designing on-chip caches. A crucial limitation of NVMs, however, is that their write endurance is low and the large intra-set write variation introduced by existing cache management policies may further exacerbate this problem, thereby reducing the cache lifetime significantly. We present EqualChance, a technique to increase cache lifetime by reducing intra-set write variation. EqualChance works by periodically changing the physical cache-block location of a write-intensive data item within a set to achieve wear-leveling. Simulations using workloads from SPEC CPU2006 suite and HPC (high-performance computing) field show that EqualChance improves the cache lifetime by 4.29X. Also, its implementation overhead is small, and it incurs very small performance and energy loss.

• Research Organization: Oak Ridge National Laboratory (ORNL)
• Sponsoring Organization: SC USDOE - Office of Science (SC)
• DOE Contract Number: AC05-00OR22725
• OSTI ID: 1159425
• Country of Publication: United States
• Language: English

Related Subjects

Non-volatile memory
ReRAM
cache lifetime
intra-set write variation
wear-leveling
write endurance