A Pixel Readout Chip in 40 nm CMOS Process for High Count Rate Imaging Systems with Minimization of Charge Sharing Effects
Conference
·
· NSS/MIC 2013 Proceedings
We present a prototype chip in 40 nm CMOS technology for readout of hybrid pixel detector. The prototype chip has a matrix of 18x24 pixels with a pixel pitch of 100 μm. It can operate both in single photon counting (SPC) mode and in C8P1 mode. In SPC the measured ENC is 84 e₋rms (for the peaking time of 48 ns), while the effective offset spread is below 2 mV rms. In the C8P1 mode the chip reconstructs full charge deposited in the detector, even in the case of charge sharing, and it identifies a pixel with the largest charge deposition. The chip architecture and preliminary measurements are reported.
- Research Organization:
- Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
- Sponsoring Organization:
- USDOE Office of Science (SC), High Energy Physics (HEP) (SC-25)
- Contributing Organization:
- Pixels Collaboration
- DOE Contract Number:
- AC02-07CH11359
- OSTI ID:
- 1151753
- Report Number(s):
- FERMILAB--PUB-13-518-PPD
- Journal Information:
- NSS/MIC 2013 Proceedings, Journal Name: NSS/MIC 2013 Proceedings Vol. C13-10-26
- Country of Publication:
- United States
- Language:
- English
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