Fast and slow border traps in MOS devices

Conference · Fri Sep 01 04:00:00 EDT 1995

OSTI ID:110801

Fleetwood, D M

Convergent lines of evidence are reviewed which show that near-interfacial oxide traps (border traps) that exchange charge with the Si can strongly affect the performance, radiation response, and long-term reliability of MOS devices. Observable effects of border traps include capacitance-voltage (C-V) hysteresis, enhanced 1/f noise, compensation of trapped holes, and increased thermally stimulated current in MOS capacitors. Effects of fast (switching times between {approximately} 10{sup {minus}6} and 1 s) and slow (switching times greater than {approximately} 1 s) border traps have been resolved via a dual-transistor technique. In conjunction with studies of MOS electrical response, electron paramagnetic resonance and spin dependent recombination studies suggest that different types of E{prime} defects (trivalent Si centers in SiO{sub 2} associated with O vacancies) can function as border traps in MOS devices exposed to ionizing radiation or high-field stress. Hydrogen-related centers may also be border traps.

• Research Organization: Sandia National Labs., Albuquerque, NM (United States)
• Sponsoring Organization: USDOE, Washington, DC (United States); Defense Nuclear Agency, Washington, DC (United States)
• DOE Contract Number: AC04-94AL85000
• OSTI ID: 110801
• Report Number(s): SAND--95-2056C; CONF-9509107--2; ON: DE95017894
• Country of Publication: United States
• Language: English

Related Subjects

36 MATERIALS SCIENCE
42 ENGINEERING
ANNEALING
DEFECTS
ELECTRICAL PROPERTIES
HYSTERESIS
MOS TRANSISTORS
RELIABILITY
SEMICONDUCTOR DEVICES