Efficient implementation techniques for gracefully degradable multiprocessor systems
- Texas A&M Univ., College Station, TX (United States)
We propose the dynamic reconfiguration network (DRN) and a monitoring-at-transmission (MAT) bus to support dynamic reconfiguration of an N-modular redundancy (NMR) multiprocessor system. In the reconfiguration process, a maximal number of processor triads are guaranteed to be formed on each processor cluster, thus supporting gracefully degradable operations. This is made possible by dynamically routing the control and clock signals of processors on the DRN so as to synchronize fault-free processors. The MAT bus is an efficient way to implement a triple modular redundant (TMR) pipeline voter (PV), which is a special case of the voting network proposed previously. Extensive experimental results have shown to support our design concept, and the performance of different cache memory organizations is evaluated through an analytic model. 22 refs.
- OSTI ID:
- 101951
- Journal Information:
- IEEE Transactions on Computers, Journal Name: IEEE Transactions on Computers Journal Issue: 4 Vol. 44; ISSN 0018-9340; ISSN ITCOB4
- Country of Publication:
- United States
- Language:
- English
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