Application of the modified voltage-dividing potentiometer to overlay metrology in a CMOS/bulk process

Conference · Mon Jan 31 23:00:00 EST 1994

OSTI ID:10132398

Allen, R A; Cresswell, M W; Linholm, L W; Owen, III, J C; Ellenwood, C H ^[1]; Hill, T A; Benecke, J D; Volk, S R; Stewart, H D ^[2]

---

1. National Inst. of Standards and Technology, Gaithersburg, MD (United States)
2. Sandia National Labs., Albuquerque, NM (United States)

The measurement of layer-to-layer feature overlay will, in the foreseeable future, continue to be a critical metrological requirement for the semiconductor industry. Meeting the image placement metrology demands of accuracy, precision, and measurement speed favors the use of electrical test structures. In this paper, a two-dimensional, modified voltage-dividing potentiometer is applied to a short-loop VLSI process to measure image placement. The contributions of feature placement on the reticle and overlay on the wafer to the overall measurement are analyzed and separated. Additional sources of uncertainty are identified, and methods developed to monitor and reduce them are described.

• Research Organization: Sandia National Labs., Albuquerque, NM (United States)
• Sponsoring Organization: USDOE, Washington, DC (United States)
• DOE Contract Number: AC04-94AL85000
• OSTI ID: 10132398
• Report Number(s): SAND--94-0405C; CONF-940369--2; ON: DE94007937; BR: GB0103012
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
426000
440800
47 OTHER INSTRUMENTATION
COMPONENTS
ELECTRON DEVICES AND CIRCUITS
FABRICATION
MASKING
MEASURING METHODS
MISCELLANEOUS INSTRUMENTATION
MONITORING
MOS TRANSISTORS
PERFORMANCE
POTENTIOMETERS
TESTING