A high performance multi-channel preamplifier ASIC
Conference
·
OSTI ID:10119190
A new preamplifier ASIC has been designed and built to improve performance of the VTPC (Vertex Time Projection Chamber) at Fermilab`s Colliding Detector Facility. Design of the semicustom IC was completed using a Tektronix Quick-Chip 2S bipolar linear array. The ASIC has 6 channels on a chip and provides lower noise, higher gain, lower power, and lower mass packaging than the device which it replaces. Actual performance of the preamplifier was found to match very closely the simulated performance. To reduce the mass of the complete circuit board, bare IC dice were mounted directly on a G-10 substrate using COB (chip on board) techniques. The preamplifier and packaging should be applicable to numerous other systems. 1 ref.
- Research Organization:
- Fermi National Accelerator Lab., Batavia, IL (United States)
- Sponsoring Organization:
- USDOE, Washington, DC (United States)
- DOE Contract Number:
- AC02-76CH03000
- OSTI ID:
- 10119190
- Report Number(s):
- FNAL/C--91/313; CONF-911106--71; ON: DE92007201
- Country of Publication:
- United States
- Language:
- English
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