Vertically integrated pixel readout chip for high energy physics
Conference
·
OSTI ID:1011163
We report on the development of the vertex detector pixel readout chips based on multi-tier vertically integrated electronics for the International Linear Collider. Some testing results of the VIP2a prototype are presented. The chip is the second iteration of the silicon implementation of the prototype, data-pushed concept of the readout developed at Fermilab. The device was fabricated in the 3D MIT-LL 0.15 {micro}m fully depleted SOI process. The prototype is a three-tier design, featuring 30 x 30 {micro}m{sup 2} pixels, laid out in an array of 48 x 48 pixels.
- Research Organization:
- Fermi National Accelerator Laboratory (FNAL), Batavia, IL
- Sponsoring Organization:
- DOE Office of Science
- DOE Contract Number:
- AC02-07CH11359
- OSTI ID:
- 1011163
- Report Number(s):
- FERMILAB-CONF-11-020-PPD
- Country of Publication:
- United States
- Language:
- English
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