Empirical Memory-Access Cost Models in Multicore NUMA Architectures

Conference · Sat Jan 01 04:00:00 EST 2011

OSTI ID:1011076

McCormick, Patrick S ^[1]; Braithwaite, Ryan Karl ^[1]; Feng, Wu-chun ^[2]

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1. Los Alamos National Laboratory
2. Virginia Tech

Data location is of prime importance when scheduling tasks in a non-uniform memory access (NUMA) architecture. The characteristics of the NUMA architecture must be understood so tasks can be scheduled onto processors that are close to the task's data. However, in modern NUMA architectures, such as AMD Magny-Cours and Intel Nehalem, there may be a relatively large number of memory controllers with sockets that are connected in a non-intuitive manner, leading to performance degradation due to uninformed task-scheduling decisions. In this paper, we provide a method for experimentally characterizing memory-access costs for modern NUMA architectures via memory latency and bandwidth microbenchmarks. Using the results of these benchmarks, we propose a memory-access cost model to improve task-scheduling decisions by scheduling tasks near the data they need. Simple task-scheduling experiments using the memory-access cost models validate the use of empirical memory-access cost models to significantly improve program performance.

• Research Organization: Los Alamos National Laboratory (LANL)
• Sponsoring Organization: DOE/LANL
• DOE Contract Number: AC52-06NA25396
• OSTI ID: 1011076
• Report Number(s): LA-UR-11-10315
• Country of Publication: United States
• Language: English

Related Subjects

BENCHMARKS
COMPUTER ARCHITECTURE
Computer Science
Mathematics & Computing (97)
PARALLEL PROCESSING
PERFORMANCE
TASK SCHEDULING