Method of forming through substrate vias (TSVs) and singulating and releasing die having the TSVs from a mechanical support substrate
Abstract
Accessing a workpiece object in semiconductor processing is disclosed. The workpiece object includes a mechanical support substrate, a release layer over the mechanical support substrate, and an integrated circuit substrate coupled over the release layer. The integrated circuit substrate includes a device layer having semiconductor devices. The method also includes etching through-substrate via (TSV) openings through the integrated circuit substrate that have buried ends at or within the release layer including using the release layer as an etch stop. TSVs are formed by introducing one or more conductive materials into the TSV openings. A die singulation trench is etched at least substantially through the integrated circuit substrate around a perimeter of an integrated circuit die. The integrated circuit die is at least substantially released from the mechanical support substrate.
- Inventors:
- Issue Date:
- Research Org.:
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1165129
- Patent Number(s):
- 8906803
- Application Number:
- 14/063,152
- Assignee:
- Sandia Corporation (Albuquerque, NM)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
- DOE Contract Number:
- AC04-94AL85000
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2013 Oct 25
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 36 MATERIALS SCIENCE; 42 ENGINEERING
Citation Formats
Okandan, Murat, and Nielson, Gregory N. Method of forming through substrate vias (TSVs) and singulating and releasing die having the TSVs from a mechanical support substrate. United States: N. p., 2014.
Web.
Okandan, Murat, & Nielson, Gregory N. Method of forming through substrate vias (TSVs) and singulating and releasing die having the TSVs from a mechanical support substrate. United States.
Okandan, Murat, and Nielson, Gregory N. Tue .
"Method of forming through substrate vias (TSVs) and singulating and releasing die having the TSVs from a mechanical support substrate". United States. https://www.osti.gov/servlets/purl/1165129.
@article{osti_1165129,
title = {Method of forming through substrate vias (TSVs) and singulating and releasing die having the TSVs from a mechanical support substrate},
author = {Okandan, Murat and Nielson, Gregory N},
abstractNote = {Accessing a workpiece object in semiconductor processing is disclosed. The workpiece object includes a mechanical support substrate, a release layer over the mechanical support substrate, and an integrated circuit substrate coupled over the release layer. The integrated circuit substrate includes a device layer having semiconductor devices. The method also includes etching through-substrate via (TSV) openings through the integrated circuit substrate that have buried ends at or within the release layer including using the release layer as an etch stop. TSVs are formed by introducing one or more conductive materials into the TSV openings. A die singulation trench is etched at least substantially through the integrated circuit substrate around a perimeter of an integrated circuit die. The integrated circuit die is at least substantially released from the mechanical support substrate.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Dec 09 00:00:00 EST 2014},
month = {Tue Dec 09 00:00:00 EST 2014}
}
Works referenced in this record:
Method of making a back contacted solar cell
patent, November 1995
- Gee, James M.
- US Patent Document 5,468,652
Method of anisotropically etching silicon
patent, March 1996
- Laermer, Franz; Schilp, Andrea
- US Patent Document 5,501,893
Method for fabricating silicon cells
patent, August 1998
- Ruby, Douglas S.; Basore, Paul Alan; Schubert, W. Kent
- US Patent Document 5,792,280
Silicon solar cells made by a self-aligned, selective-emitter, plasma-etchback process
patent, February 1999
- Ruby, Douglas S.; Schubert, William K.; Gee, James M.
- US Patent Document 5,871,591
High-efficiency solar cell and method for fabrication
patent, August 1999
- Hou, Hong Q.; Reinhardt, Kitt
- US Patent Document 5,944,913
Laminated photovoltaic modules using back-contact solar cells
patent, September 1999
- Gee, James M.; Garrett, Stephen; Morgan, William P.
- US Patent Document 5,951,786
Method of monolithic module assembly
patent, October 1999
- Gee, James M.; Garrett, Stephen; Morgan, William P.
- US Patent Document 5,972,732
Silicon cells made by self-aligned selective-emitter plasma-etchback process
patent, July 2000
- Ruby, Douglas S.; Schubert, William K.; Gee, James M.
- US Patent Document 6,091,021
InGaAsN/GaAs heterojunction for multi-junction solar cells
patent, June 2001
- Kurtz, Steven R.; Allerman, Andrew A.; Klem, John F.
- US Patent Document 6,252,287
Methods relating to trench-based support structures for semiconductor devices
patent, April 2011
- Sonsky, Jan; Van Noort, Wibo D.
- US Patent Document 7,923,345
Through substrate vias for back-side interconnections on very thin semiconductor wafers
patent, May 2011
- Ramiah, Chandrasekaram; Mitchell, Douglas G.; Petras, Michael F.
- US Patent Document 7,935,571
Semiconductor die singulation method
patent, August 2011
- Grivna, Gordon M.; Seddon, Michael J.
- US Patent Document 7,989,319
Die singulation method and package formed thereby
patent, August 2012
- Anderson, Robert C.; Shul, Randy J.; Clews, Peggy J.
- US Patent Document 8,236,611
Stacked die assemblies including TSV die
patent, November 2012
- Dunne, Rajiv; Simmons-Matthews, Margaret
- US Patent Document 8,313,982
3-D circuits with integrated passive devices
patent, January 2013
- Sanders, Paul W.; Jones, Robert E.; Petras, Michael F.
- US Patent Document 8,344,503
Die singulation method
patent, June 2013
- Swiler, Thomas P.; Garcia, Ernest J.; Francis, Kathryn M.
- US Patent Document 8,461,023
Lead Frame and Method of Forming Same
patent-application, March 2011
- Gao, Xu; He, Qingchun; Xu, Nan
- US Patent Application 12/578556; 20110065240
Integrated Circuit Packaging System with Package-on-Package Stacking and Method of Manufacture Thereof
patent-application, April 2011
- Park, HyungSang; Yang, Deok Kyung; Choi, Dae Sik
- US Patent Application 12/580933; 20110089552
Pass-Through 3D Interconnect for Microelectronics Dies and Associated Systems and Methods
patent-application, April 2012
- Pratt, David S.; Kirby, Kyle K.; Ray, Dewali
- US Patent Application 13/335619; 20120094443
Multi-Layer Interconnect Structure for Stacked Dies
patent-application, January 2013
- Chang, Hung-Pin; Chiu, Chien-Ming; Wu, Tsang-Jiuh
- US Patent Application 13/608456; 20130001799
Works referencing / citing this record:
Fast process flow, on-wafer interconnection and singulation for MEPV
patent, January 2017
- Okandan, Murat; Nielson, Gregory N.; Cruz-Campa, Jose Luis
- US Patent Document 9,559,219
Separating semiconductor devices from substrate by etching graded composition release layer disposed between semiconductor devices and substrate including forming protuberances that reduce stiction
patent, May 2015
- Tauke-Pedretti, Anna; Nielson, Gregory N.; Cederberg, Jeffrey
- US Patent Document 9,029,239