Leadless chip carrier packaging and cad/cam-supported wire wrap interconnect technology for subnanosecond ecl. Interim report 1 jul 80-30 jun 81
This report describes the results of work conducted to develop rapid methods for designing and prototyping high-speed digital processor systems using subnanosecond emitter coupled logic (ECL). In Task I, we have begun a conversion of the design rules, interconnection protocols, special components, and standard logic panels developed during the first year for high-speed ECL-based digital processors from a technology based upon dual-in-line packages (DIP) to a technology based upon specially designed leadless ceramic chip carriers. This conversion was undertaken since it was learned during the first year that the DIP packages themselves are compromising the maximum performance levels of which the ECL dice are capable. We have also undertaken an extensive investigation of several possible approaches to increasing these operational maxima to an even greater extent than with our present design for new Leadless Ceramic Chip Carriers. Task 2 was to continue development of a comprehensive computer-aided design/computer-aided manufacturing (CAD/CAM) software package which would be specifically tailored to support the peculiar design requirements of processors operating in a high clock rate, transmission line environment. The CAD/CAM software package has been structured to be sufficiently flexible to assimilate advances in device and component technology, and to accept new sets of design rules resulting from advances in engineering design practice.
- Research Organization:
- National Building Research Inst., Pretoria (South Africa)
- OSTI ID:
- 7032901
- Report Number(s):
- AD-A-113082/2
- Country of Publication:
- United States
- Language:
- English
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