Combating the Reliability Challenge of GPU Register File at Low Supply Voltage

Conference · Sun Sep 11 00:00:00 EDT 2016

DOI:https://doi.org/10.1145/2967938.2967951· OSTI ID:1339050

Tan, Jingweijia; Song, Shuaiwen; Yan, Kaige; Fu, Xin; Marquez, Andres; Kerbyson, Darren J.

Supply voltage reduction is an effective approach to significantly reduce GPU energy consumption. As the largest on-chip storage structure, the GPU register file becomes the reliability hotspot that prevents further supply voltage reduction below the safe limit (Vmin) due to process variation effects. This work addresses the reliability challenge of the GPU register file at low supply voltages, which is an essential first step for aggressive supply voltage reduction of the entire GPU chip. We propose GR-Guard, an architectural solution that leverages long register dead time to enable reliable operations from unreliable register file at low voltages.

• Research Organization: Pacific Northwest National Lab. (PNNL), Richland, WA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC05-76RL01830
• OSTI ID: 1339050
• Report Number(s): PNNL-SA-119484; KJ0402000
• Resource Relation: Conference: Proceedings of the 25th International Conference on Parallel Architectures and Compilation (PACT '16), September 11-15, 2016, Haifa, Israel, 3-15
• Country of Publication: United States
• Language: English

Related Subjects

Energy-efficient design
Architecture-Compiler co-design
low voltage GPU