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Title: Extensible packet processing architecture

A technique for distributed packet processing includes sequentially passing packets associated with packet flows between a plurality of processing engines along a flow through data bus linking the plurality of processing engines in series. At least one packet within a given packet flow is marked by a given processing engine to signify by the given processing engine to the other processing engines that the given processing engine has claimed the given packet flow for processing. A processing function is applied to each of the packet flows within the processing engines and the processed packets are output on a time-shared, arbitered data bus coupled to the plurality of processing engines.
Authors:
; ; ; ;
Publication Date:
OSTI Identifier:
1093265
Report Number(s):
8,514,855
12/773,120
DOE Contract Number:
AC04-94AL85000
Resource Type:
Patent
Research Org:
SNL-A (Sandia National Laboratories, Albuquerque, NM (United States))
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING