Title: Reoptimization of Quantum Circuits via Hierarchical Synthesis

Abstract

The current phase of quantum computing is in the Noisy Intermediate-Scale Quantum (NISQ) era. On NISQ devices, two-qubit gates such as CNOTs are much noisier than single-qubit gates, so it is essential to minimize their count. Quantum circuit synthesis is a process of decomposing an arbitrary unitary into a sequence of quantum gates, and can be used as an optimization tool to produce shorter circuits to improve overall circuit fidelity. However, the time-to-solution of synthesis grows exponentially with the number of qubits. As a result, synthesis is intractable for circuits on a large qubit scale. In this paper, we propose a hierarchical, block-by-block opti-mization framework, QGo, for quantum circuit optimization. Our approach allows an exponential cost optimization to scale to large circuits. QGo uses a combination of partitioning and synthesis: 1) partition the circuit into a sequence of independent circuit blocks; 2) re-generate and optimize each block using quantum synthesis; and 3) re-compose the final circuit by stitching all the blocks together. We perform our analysis and show the fidelity improvements in three different regimes: small-size circuits on real devices, medium-size circuits on noisy simulations, and large-size circuits on analytical models. Our technique can be applied after existing optimizations tomore » achieve higher circuit fidelity. Further, using a set of NISQ benchmarks, we show that QGo can reduce the number of CNOT gates by 29.9% on average and up to 50% when compared with industrial compiler optimizations such as t|ket). When executed on the IBM Athens system, shorter depth leads to higher circuit fidelity. We also demonstrate the scalability of our QGo technique to optimize circuits of 60+ qubits, Our technique is the first demonstration of successfully employing and scaling synthesis in the compilation tool chain for large circuits. Overall, our approach is robust for direct incorporation in production compiler toolchains to further improve the circuit fidelity.« less

Authors:

Wu, Xin-Chuan ^[1]; Davis, Marc Grau ^[2]; Chong, Frederic T. ^[3]; Iancu, Costin ^[4]

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+ Show Author Affiliations

1. Corp., Santa Clara, CA (United States)
2. Massachusetts Inst. of Technology (MIT), Cambridge, MA (United States)
3. Univ. of Chicago, IL (United States)
4. Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)

Publication Date:

Mon Nov 01 00:00:00 EDT 2021

Research Org.:

Univ. of Chicago, IL (United States)

Sponsoring Org.:

USDOE Office of Science (SC), Engineering & Technology

OSTI Identifier:

1865293

Grant/Contract Number:  

SC0020289

Resource Type:

Accepted Manuscript

Journal Name:

2021 International Conference on Rebooting Computing (ICRC)

Additional Journal Information:

Journal Name: 2021 International Conference on Rebooting Computing (ICRC); Journal Volume: 2021; Conference: 2021 International Conference on Rebooting Computing (ICRC), Los Alamitos (held virtually), CA (United States), 30 Nov - 2 Dec 2021

Publisher:

IEEE

Country of Publication:

United States

Language:

English

Subject:

97 MATHEMATICS AND COMPUTING; Analytical models; Circuit optimization; Scalability; Qubit; Production; Logic gates; Noise measurement