Robust Duplication with Comparison Methods in Microcontrollers
Commercial microprocessors could be useful computational platforms in space systems, as long as the risk is bound. Many spacecraft are computationally constrained because all of the computation is done on a single radiation-hardened microprocessor. It is possible that a commercial microprocessor could be used for configuration, monitoring and background tasks that are not mission critical. Most commercial microprocessors are affected by radiation, including single-event effects (SEEs) that could be destructive to the component or corrupt the data. Part screening can help designers avoid components with destructive failure modes, and mitigation can suppress data corruption. We have been experimenting with a method for masking radiation-induced faults through the software executing on the microprocessor. While triple-modular redundancy (TMR) techniques are very effective at masking faults in software, the increased amount of execution time to complete the computation is not desirable. Here in this article we present a technique for combining duplication with compare (DWC) with TMR that decreases observable errors by as much as 145 times with only a 2.35 time decrease in performance.
- Research Organization:
- Los Alamos National Laboratory (LANL)
- Sponsoring Organization:
- USDOE National Nuclear Security Administration (NNSA). Office of Defense Nuclear Nonproliferation (NA-20)
- Grant/Contract Number:
- AC52-06NA25396
- OSTI ID:
- 1345154
- Report Number(s):
- LA-UR-16-24797
- Journal Information:
- IEEE Transactions on Nuclear Science, Journal Name: IEEE Transactions on Nuclear Science Journal Issue: 1 Vol. 64; ISSN 0018-9499; ISSN 1558-1578
- Publisher:
- Institute of Electrical and Electronics Engineers (IEEE)Copyright Statement
- Country of Publication:
- United States
- Language:
- English
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