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Title: A survey of techniques for architecting and managing GPU register file

Abstract

To support their massively-multithreaded architecture, GPUs use very large register file (RF) which has a capacity higher than even L1 and L2 caches. In total contrast, traditional CPUs use tiny RF and much larger caches to optimize latency. Due to these differences, along with the crucial impact of RF in determining GPU performance, novel and intelligent techniques are required for managing GPU RF. In this paper, we survey the techniques for designing and managing GPU RF. We discuss techniques related to performance, energy and reliability aspects of RF. To emphasize the similarities and differences between the techniques, we classify them along several parameters. Lastly, the aim of this paper is to synthesize the state-of-art developments in RF management and also stimulate further research in this area.

Authors:
ORCiD logo [1]
  1. Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)
Publication Date:
Research Org.:
Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)
Sponsoring Org.:
USDOE Office of Science (SC)
OSTI Identifier:
1332070
Grant/Contract Number:  
AC05-00OR22725
Resource Type:
Accepted Manuscript
Journal Name:
IEEE Transactions on Parallel and Distributed Systems
Additional Journal Information:
Journal Volume: 27; Journal Issue: 6; Journal ID: ISSN 1045-9219
Publisher:
IEEE
Country of Publication:
United States
Language:
English
Subject:
32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATION; review; classification; GPGPU; GPU; register file; reliability; performance; power management; non-volatile memory; embedded DRAM (eDRAM)

Citation Formats

Mittal, Sparsh. A survey of techniques for architecting and managing GPU register file. United States: N. p., 2016. Web. doi:10.1109/TPDS.2016.2546249.
Mittal, Sparsh. A survey of techniques for architecting and managing GPU register file. United States. doi:10.1109/TPDS.2016.2546249.
Mittal, Sparsh. Thu . "A survey of techniques for architecting and managing GPU register file". United States. doi:10.1109/TPDS.2016.2546249. https://www.osti.gov/servlets/purl/1332070.
@article{osti_1332070,
title = {A survey of techniques for architecting and managing GPU register file},
author = {Mittal, Sparsh},
abstractNote = {To support their massively-multithreaded architecture, GPUs use very large register file (RF) which has a capacity higher than even L1 and L2 caches. In total contrast, traditional CPUs use tiny RF and much larger caches to optimize latency. Due to these differences, along with the crucial impact of RF in determining GPU performance, novel and intelligent techniques are required for managing GPU RF. In this paper, we survey the techniques for designing and managing GPU RF. We discuss techniques related to performance, energy and reliability aspects of RF. To emphasize the similarities and differences between the techniques, we classify them along several parameters. Lastly, the aim of this paper is to synthesize the state-of-art developments in RF management and also stimulate further research in this area.},
doi = {10.1109/TPDS.2016.2546249},
journal = {IEEE Transactions on Parallel and Distributed Systems},
number = 6,
volume = 27,
place = {United States},
year = {2016},
month = {4}
}

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Works referencing / citing this record:

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