Title: Evaluating cyber-risk in synchrophasor systems

Abstract

Technology related to evaluating cyber-risk for synchrophasor systems is disclosed. In one example of the disclosed technology, a method includes generating an event tree model of a timing-attack on a synchrophasor system architecture. The event tree model can be based on locations and types of timing-attacks, an attack likelihood, vulnerabilities and detectability along a scenario path, and consequences of the timing-attack. A cyber-risk score of the synchrophasor system architecture can be determined using the event tree model. The synchrophasor system architecture can be adapted in response to the cyber-risk score.

Inventors:

Pal, Seemita; Veeramany, Arun; Bonebrake, Christopher A.; Johnson, Beverly E.; Hutton, III, William James; Sridhar, Siddharth; Gourisetti, Sri Nikhil Gupta; Coles, Garill A.

Issue Date:

Tue Dec 21 00:00:00 EST 2021

Research Org.:

Pacific Northwest National Laboratory (PNNL), Richland, WA (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1860192

Patent Number(s):

11206287

Application Number:

16/261,283

Assignee:

Battelle Memorial Institute (Richland, WA)

Patent Classifications (CPCs):

H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION

Show more

H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION

H04L2463/121 - Timestamp
H04L63/1433 - {Vulnerability analysis}
H04L63/1466 - {Active attacks involving interception, injection, modification, spoofing of data unit addresses, e.g. hijacking, packet injection or TCP sequence number attacks}

Show less

DOE Contract Number:  

AC05-76RL01830

Resource Type:

Patent

Resource Relation:

Patent File Date: 01/29/2019

Country of Publication:

United States

Language:

English