Global synchronization of parallel processors using clock pulse width modulation
Abstract
A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.
- Inventors:
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1083810
- Patent Number(s):
- 8412974
- Application Number:
- 12/696,764
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- DOE Contract Number:
- B554331
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Chen, Dong, Ellavsky, Matthew R., Franke, Ross L., Gara, Alan, Gooding, Thomas M., Haring, Rudolf A., Jeanson, Mark J., Kopcsay, Gerard V., Liebsch, Thomas A., Littrell, Daniel, Ohmacht, Martin, Reed, Don D., Schenck, Brandon E., and Swetz, Richard A. Global synchronization of parallel processors using clock pulse width modulation. United States: N. p., 2013.
Web.
Chen, Dong, Ellavsky, Matthew R., Franke, Ross L., Gara, Alan, Gooding, Thomas M., Haring, Rudolf A., Jeanson, Mark J., Kopcsay, Gerard V., Liebsch, Thomas A., Littrell, Daniel, Ohmacht, Martin, Reed, Don D., Schenck, Brandon E., & Swetz, Richard A. Global synchronization of parallel processors using clock pulse width modulation. United States.
Chen, Dong, Ellavsky, Matthew R., Franke, Ross L., Gara, Alan, Gooding, Thomas M., Haring, Rudolf A., Jeanson, Mark J., Kopcsay, Gerard V., Liebsch, Thomas A., Littrell, Daniel, Ohmacht, Martin, Reed, Don D., Schenck, Brandon E., and Swetz, Richard A. Tue .
"Global synchronization of parallel processors using clock pulse width modulation". United States. https://www.osti.gov/servlets/purl/1083810.
@article{osti_1083810,
title = {Global synchronization of parallel processors using clock pulse width modulation},
author = {Chen, Dong and Ellavsky, Matthew R. and Franke, Ross L. and Gara, Alan and Gooding, Thomas M. and Haring, Rudolf A. and Jeanson, Mark J. and Kopcsay, Gerard V. and Liebsch, Thomas A. and Littrell, Daniel and Ohmacht, Martin and Reed, Don D. and Schenck, Brandon E. and Swetz, Richard A.},
abstractNote = {A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Apr 02 00:00:00 EDT 2013},
month = {Tue Apr 02 00:00:00 EDT 2013}
}
Works referenced in this record:
Microprocessor clocking control system
patent, May 1999
- Casal, Humberto Felipe
- US Patent Document 5,903,747
Multiple channel synchronized clock generation scheme
patent, August 2011
- Kocaman, Namik; Momtaz, Afshin
- US Patent Document 7,991,101
Method and apparatus for determining jitter and pulse width from clock signal comparisons
patent, October 2007
- Cranford, Jr., Hayden C.; Gebara, Fadi H.; Schaub, Jeremy D.
- US Patent Document 7,286,947
Performance monitor synchronization in a multiprocessor system
patent, November 2002
- Rawson, III, Freeman Leigh
- US Patent Document 6,480,966
Method for shrinking a clock cycle when testing high speed microprocessor designs
patent, August 1997
- Yip, Chung Yin; Wegman, Marc E.
- US Patent Document 5,661,731
On-die automatic selection of manipulated clock pulse
patent, May 2005
- Slawecki, Darren; Rotter, Stephan
- US Patent Document 6,892,157
Multi-Petascale Highly Efficient Parallel Supercomputer
patent-application, September 2011
- Asaad, Sameh; Bellofatto, Ralph E.; Blocksome, Michael A.
- US Patent Document 13/004007; 20110219208
Apparatus and method for reducing power consumption in microprocessors through selective gating of clock signals
patent, September 1998
- Feierbach, Gary F.
- US Patent Document 5,815,725
Circuit for generating a stretched clock signal by one period or one-half period
patent, May 1994
- Lee, Robert H.; Kenny, John D.
- US Patent Document 5,313,108
Synchronizing processors when entering system management mode
patent, August 2011
- Diaz, Juan F.; Herzi, Dirie N.; Volentine, Robert
- US Patent Document 7,991,933
Method and apparatus for varying a clock frequency on a phase by phase basis
patent, October 2000
- Stinson, Jason C.; Lilya, Edwin R.; Nazareth, Mathew
- US Patent Document 6,127,858
Low skew minimized clock splitter
patent, October 2002
- Vakil, Kersi H.; Roy, William N.; Jex, Jerry G.
- US Patent Document 6,466,074
Circuit for generating stretched clock phases on a cycle by cycle basis
patent, September 1991
- Fitch, Jonathan
- US Patent Document 5,045,715
Manipulating an integrated circuit clock in response to early detection of an operation known to trigger an internal disturbance
patent, October 2004
- Josephson, Don D.; Naffziger, Samuel D.
- US Patent Document 6,804,793