Modular high speed counter employing edge-triggered code
Abstract
A high speed modular counter (100) utilizing a novel counting method in which the first bit changes with the frequency of the driving clock, and changes in the higher order bits are initiated one clock pulse after a 0'' to 1'' transition of the next lower order bit. This allows all carries to be known one clock period in advance of a bit change. The present counter is modular and utilizes two types of standard counter cells. A first counter cell determines the zero bit. The second counter cell determines any other higher order bit. Additional second counter cells are added to the counter to accommodate any count length without affecting speed.
- Inventors:
- Issue Date:
- Research Org.:
- Universities Research Association, Inc., Washington, DC (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 5987857
- Patent Number(s):
- 5224133
- Application Number:
- PPN: US 7-847912
- Assignee:
- Universities Research Association, Inc., Washington, DC (United States)
- DOE Contract Number:
- AC02-89ER40486
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 6 Mar 1992
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 42 ENGINEERING; COUNTING CIRCUITS; DESIGN; DIGITAL SYSTEMS; MODULAR STRUCTURES; PERFORMANCE; ELECTRONIC CIRCUITS; 426000* - Engineering- Components, Electron Devices & Circuits- (1990-)
Citation Formats
Vanstraelen, G F. Modular high speed counter employing edge-triggered code. United States: N. p., 1993.
Web.
Vanstraelen, G F. Modular high speed counter employing edge-triggered code. United States.
Vanstraelen, G F. Tue .
"Modular high speed counter employing edge-triggered code". United States.
@article{osti_5987857,
title = {Modular high speed counter employing edge-triggered code},
author = {Vanstraelen, G F},
abstractNote = {A high speed modular counter (100) utilizing a novel counting method in which the first bit changes with the frequency of the driving clock, and changes in the higher order bits are initiated one clock pulse after a 0'' to 1'' transition of the next lower order bit. This allows all carries to be known one clock period in advance of a bit change. The present counter is modular and utilizes two types of standard counter cells. A first counter cell determines the zero bit. The second counter cell determines any other higher order bit. Additional second counter cells are added to the counter to accommodate any count length without affecting speed.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Jun 29 00:00:00 EDT 1993},
month = {Tue Jun 29 00:00:00 EDT 1993}
}
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