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Title: Modular high speed counter employing edge-triggered code

Abstract

A high speed modular counter (100) utilizing a novel counting method in which the first bit changes with the frequency of the driving clock, and changes in the higher order bits are initiated one clock pulse after a "0" to "1" transition of the next lower order bit. This allows all carries to be known one clock period in advance of a bit change. The present counter is modular and utilizes two types of standard counter cells. A first counter cell determines the zero bit. The second counter cell determines any other higher order bit. Additional second counter cells are added to the counter to accommodate any count length without affecting speed.

Inventors:
 [1]
  1. DeSoto, TX
Issue Date:
Research Org.:
Universities Research Association, Inc. (Washington, DC)
Sponsoring Org.:
USDOE
OSTI Identifier:
868835
Patent Number(s):
5224133
Assignee:
Universities Research Association, Inc. (Washington, DC)
Patent Classifications (CPCs):
H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
DOE Contract Number:  
AC02-89ER40486
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
modular; speed; counter; employing; edge-triggered; code; 100; utilizing; novel; counting; method; bit; changes; frequency; driving; clock; bits; initiated; pulse; transition; allows; carries; period; advance; change; utilizes; types; standard; cells; cell; determines; zero; additional; added; accommodate; count; length; affecting; clock pulse; /377/

Citation Formats

Vanstraelen, Guy F. Modular high speed counter employing edge-triggered code. United States: N. p., 1993. Web.
Vanstraelen, Guy F. Modular high speed counter employing edge-triggered code. United States.
Vanstraelen, Guy F. Tue . "Modular high speed counter employing edge-triggered code". United States. https://www.osti.gov/servlets/purl/868835.
@article{osti_868835,
title = {Modular high speed counter employing edge-triggered code},
author = {Vanstraelen, Guy F},
abstractNote = {A high speed modular counter (100) utilizing a novel counting method in which the first bit changes with the frequency of the driving clock, and changes in the higher order bits are initiated one clock pulse after a "0" to "1" transition of the next lower order bit. This allows all carries to be known one clock period in advance of a bit change. The present counter is modular and utilizes two types of standard counter cells. A first counter cell determines the zero bit. The second counter cell determines any other higher order bit. Additional second counter cells are added to the counter to accommodate any count length without affecting speed.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1993},
month = {6}
}

Patent:

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