Memory system for a data processing network
Abstract
A data processing network includes a network of devices addressable via a system address space, the network including a computing device configured to execute an application in a virtual address space. A virtual-to-system address translation circuit is configured to translate a virtual address to a system address. A memory node controller has a first interface to a data resource addressable via a physical address space, a second interface to the computing device, and a system-to-physical address translation circuit, configured to translate a system address in the system address space to a corresponding physical address in the physical address space of the data resource. The virtual-to-system mapping may be a range table buffer configured to retrieve a range table entry comprising an offset address of a range together with a virtual address base and an indicator of the extent of the range.
- Inventors:
- Issue Date:
- Research Org.:
- Arm Ltd., Cambridge (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1632438
- Patent Number(s):
- 10534719
- Application Number:
- 15/819,328
- Assignee:
- Arm Limited (Cambridge, GB)
- Patent Classifications (CPCs):
-
G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 11/21/2017
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Beard, Jonathan Curtis, Rusitoru, Roxana, and Dunham, Curtis Glenn. Memory system for a data processing network. United States: N. p., 2020.
Web.
Beard, Jonathan Curtis, Rusitoru, Roxana, & Dunham, Curtis Glenn. Memory system for a data processing network. United States.
Beard, Jonathan Curtis, Rusitoru, Roxana, and Dunham, Curtis Glenn. Tue .
"Memory system for a data processing network". United States. https://www.osti.gov/servlets/purl/1632438.
@article{osti_1632438,
title = {Memory system for a data processing network},
author = {Beard, Jonathan Curtis and Rusitoru, Roxana and Dunham, Curtis Glenn},
abstractNote = {A data processing network includes a network of devices addressable via a system address space, the network including a computing device configured to execute an application in a virtual address space. A virtual-to-system address translation circuit is configured to translate a virtual address to a system address. A memory node controller has a first interface to a data resource addressable via a physical address space, a second interface to the computing device, and a system-to-physical address translation circuit, configured to translate a system address in the system address space to a corresponding physical address in the physical address space of the data resource. The virtual-to-system mapping may be a range table buffer configured to retrieve a range table entry comprising an offset address of a range together with a virtual address base and an indicator of the extent of the range.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2020},
month = {1}
}
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