Method of synchronizing independent functional unit

Kim, Changhoan

Title: Method of synchronizing independent functional unit

Abstract

A system for synchronizing parallel processing of a plurality of functional processing units (FPU), a first FPU and a first program counter to control timing of a first stream of program instructions issued to the first FPU by advancement of the first program counter; a second FPU and a second program counter to control timing of a second stream of program instructions issued to the second FPU by advancement of the second program counter, the first FPU is in communication with a second FPU to synchronize the issuance of a first stream of program instructions to the second stream of program instructions and the second FPU is in communication with the first FPU to synchronize the issuance of the second stream program instructions to the first stream of program instructions.

Inventors:: Kim, Changhoan

Issue Date:: 2017-05-16

Research Org.:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1357500

Patent Number(s):: 9652235

Application Number:: 14/950,452

Assignee:: International Business Machines Corporation

Patent Classifications (CPCs):: G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING

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G - PHYSICS G06 - COMPUTING G06F - ELECTRIC DIGITAL DATA PROCESSING
G06F12/0875 - with dedicated cache, e.g. instruction or stack
G06F2212/452 - Instruction code
G06F9/3005 - {to perform operations for flow control}
G06F9/30087 - {Synchronisation or serialisation instructions}
G06F9/3009 - {Thread control instructions}
G06F9/321 - {Program or instruction counter, e.g. incrementing}
G06F9/3851 - {from multiple instruction streams, e.g. multistreaming
G06F9/3885 - {using a plurality of independent parallel functional units}

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DOE Contract Number:: B599858

Resource Type:: Patent

Resource Relation:: Patent File Date: 2015 Nov 24

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Kim, Changhoan. Method of synchronizing independent functional unit.  United States: N. p., 2017. 
        Web.

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                    Kim, Changhoan. Method of synchronizing independent functional unit.  United States.

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                    Kim, Changhoan. Tue .  
        "Method of synchronizing independent functional unit".  United States.  https://www.osti.gov/servlets/purl/1357500.

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@article{osti_1357500,

  title        = {Method of synchronizing independent functional unit},

  author       = {Kim, Changhoan},

  abstractNote = {A system for synchronizing parallel processing of a plurality of functional processing units (FPU), a first FPU and a first program counter to control timing of a first stream of program instructions issued to the first FPU by advancement of the first program counter; a second FPU and a second program counter to control timing of a second stream of program instructions issued to the second FPU by advancement of the second program counter, the first FPU is in communication with a second FPU to synchronize the issuance of a first stream of program instructions to the second stream of program instructions and the second FPU is in communication with the first FPU to synchronize the issuance of the second stream program instructions to the first stream of program instructions.},

  doi          = {},

  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2017},

  month        = {5}

}

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Similar Records

Title: Method of synchronizing independent functional unit

Abstract

Citation Formats

Method and system using tagged instructions to allow out-of-program-order instruction decoding patent, April 2001

Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism patent, November 2001

Input replicator for interrupts in a simultaneous and redundantly threaded processor patent, September 2004

Apparatus and method for synchronizing multiple threads in an out-of-order microprocessor patent, February 2009

Managing cache memory in a parallel processing environment patent, January 2014

Programmable streaming processor with mixed precision instruction execution patent, January 2014

Variable clocked heterogeneous serial array processor patent, February 2014

GPU pipeline synchronization and control system and method patent, August 2014

Logic for Synchronizing Multiple Tasks at Multiple Locations in an Instruction Stream patent-application, December 2008

Method And Apparatus For Scheduling Of Instructions In A Multi-Strand Out-Of-Order Processor patent-application, January 2013

Instruction recycling on a multiple-path processor conference, January 1999

The StageNet fabric for constructing resilient multicore systems conference, November 2008

Method and system using tagged instructions to allow out-of-program-order instruction decoding
patent, April 2001

Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism
patent, November 2001

Input replicator for interrupts in a simultaneous and redundantly threaded processor
patent, September 2004

Apparatus and method for synchronizing multiple threads in an out-of-order microprocessor
patent, February 2009

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patent, January 2014

Programmable streaming processor with mixed precision instruction execution
patent, January 2014

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patent, February 2014

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patent-application, January 2013

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conference, November 2008