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Title: Method of synchronizing independent functional unit

A system for synchronizing parallel processing of a plurality of functional processing units (FPU), a first FPU and a first program counter to control timing of a first stream of program instructions issued to the first FPU by advancement of the first program counter; a second FPU and a second program counter to control timing of a second stream of program instructions issued to the second FPU by advancement of the second program counter, the first FPU is in communication with a second FPU to synchronize the issuance of a first stream of program instructions to the second stream of program instructions and the second FPU is in communication with the first FPU to synchronize the issuance of the second stream program instructions to the first stream of program instructions.
Inventors:
Issue Date:
OSTI Identifier:
1343756
Assignee:
International Business Machines Corporation OSTI
Patent Number(s):
9,569,215
Application Number:
15/237,026
Contract Number:
B599858
Resource Relation:
Patent File Date: 2016 Aug 15
Research Org:
International Business Machines Corporation, Armonk, NY (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Other works cited in this record:

Method and system using tagged instructions to allow out-of-program-order instruction decoding
patent, April 2001

Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism
patent, November 2001

Input replicator for interrupts in a simultaneous and redundantly threaded processor
patent, September 2004

Apparatus and method for synchronizing multiple threads in an out-of-order microprocessor
patent, February 2009

Managing cache memory in a parallel processing environment
patent, January 2014

Programmable streaming processor with mixed precision instruction execution
patent, January 2014

Variable clocked heterogeneous serial array processor
patent, February 2014

GPU pipeline synchronization and control system and method
patent, August 2014

Instruction recycling on a multiple-path processor
conference, January 1999
  • Wallace, S.; Tullsen, D. M.; Calder, B.
  • High-Performance Computer Architecture, 1999. Proceedings. Fifth International Symposium On
  • DOI: 10.1109/HPCA.1999.744323

The StageNet fabric for constructing resilient multicore systems
conference, November 2008
  • Gupta, Shantanu; Feng, Shuguang; Ansari, Amin
  • Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on
  • DOI: 10.1109/MICRO.2008.4771786

An Efficient Algorithm for Exploiting Multiple Arithmetic Units
journal, January 1967
  • Tomasulo, R. M.
  • IBM Journal of Research and Development, Vol. 11, Issue 1, p. 25-33
  • DOI: 10.1147/rd.111.0025

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