Implementing inverted master-slave 3D semiconductor stack
Abstract
A method and apparatus are provided for implementing an enhanced three dimensional (3D) semiconductor stack. A chip carrier has an aperture of a first length and first width. A first chip has at least one of a second length greater than the first length or a second width greater than the first width; a second chip attached to the first chip, the second chip having at least one of a third length less than the first length or a third width less than the first width; the first chip attached to the chip carrier by connections in an overlap region defined by at least one of the first and second lengths or the first and second widths; the second chip extending into the aperture; and a heat spreader attached to the chip carrier and in thermal contact with the first chip for dissipating heat from both the first chip and second chip.
- Inventors:
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1241310
- Patent Number(s):
- 9281302
- Application Number:
- 14/184,868
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES
- DOE Contract Number:
- B601996
- Resource Type:
- Patent
- Resource Relation:
- Patent File Date: 2014 Feb 20
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING; 42 ENGINEERING
Citation Formats
Coteus, Paul W., Hall, Shawn A., and Takken, Todd E. Implementing inverted master-slave 3D semiconductor stack. United States: N. p., 2016.
Web.
Coteus, Paul W., Hall, Shawn A., & Takken, Todd E. Implementing inverted master-slave 3D semiconductor stack. United States.
Coteus, Paul W., Hall, Shawn A., and Takken, Todd E. Tue .
"Implementing inverted master-slave 3D semiconductor stack". United States. https://www.osti.gov/servlets/purl/1241310.
@article{osti_1241310,
title = {Implementing inverted master-slave 3D semiconductor stack},
author = {Coteus, Paul W. and Hall, Shawn A. and Takken, Todd E.},
abstractNote = {A method and apparatus are provided for implementing an enhanced three dimensional (3D) semiconductor stack. A chip carrier has an aperture of a first length and first width. A first chip has at least one of a second length greater than the first length or a second width greater than the first width; a second chip attached to the first chip, the second chip having at least one of a third length less than the first length or a third width less than the first width; the first chip attached to the chip carrier by connections in an overlap region defined by at least one of the first and second lengths or the first and second widths; the second chip extending into the aperture; and a heat spreader attached to the chip carrier and in thermal contact with the first chip for dissipating heat from both the first chip and second chip.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Mar 08 00:00:00 EST 2016},
month = {Tue Mar 08 00:00:00 EST 2016}
}
Works referenced in this record:
Semiconductor chip carrier package with a heat sink
patent, December 1986
- Stenerson, Gary L.; Miller, Thomas
- US Patent Document 4,630,172
Stacked silicon die carrier assembly
patent, July 1995
- Shokrgozar, Hamid; Reeves, Leonard; Heggli, Bjarne
- US Patent Document 5,434,745
High density integrated circuit module
patent, July 2005
- Burns, Carmen D.
- US Patent Document 6,919,626
Method and system for stacking integrated circuits
patent, April 2010
- Jensen, Ronald J.; Heikkila, Walter W.
- US Patent Document 7,700,409
Semiconductor device and method of stacking same size semiconductor die electrically connected through conductive via formed around periphery of the die
patent, November 2011
- Do, Byung Tai; Kuan, Heap Hoe; Chow, Seng Guan
- US Patent Document 8,062,929
Implementing multiple different types of dies for memory stacking
patent, January 2013
- Coteus, Paul W.; Kim, Kyu-hyoun
- US Patent Document 8,343,804
Implementing vertical die stacking to distribute logical function over multiple dies in through-silicon-via stacked semiconductor device
patent, August 2013
- Coteus, Paul W.; Kim, Kyu-hyoun; Tremaine, Robert B.
- US Patent Document 8,516,409
Mountable Integrated Circuit Package System with Intra-Stack Encapsulation
patent-application, July 2009
- Kim, Youngjoon; Park, Soo-San
- US Patent Application 11/965653; 20090166886
Packaged Semiconductor Device for High Performance Memory and Logic
patent-application, July 2012
- Li, Ming
- US Patent Application 13/387702; 20120187578
Stacked Semiconductor Devices Including a Master Device
patent-application, April 2013
- Kim, Jin-Ki
- US Patent Application 13/713320; 20130102111
Semiconductor Die Assemblies with Enhanced Thermal Management, Semiconductor Devices Including Same and Related Methods
patent-application, May 2013
- Luo, Shijian; Li, Xiao; Li, Jian
- US Patent Application 13/613,235; 2013/0119527 Al
Power Distribution for 3D Semiconductor Package
patent-application, April 2015
- Lamorey, Mark C.; Patel, Janak G.; Slota, JR., Peter
- US Patent Application 14/041277; 20150091131