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Title: Implementing inverted master-slave 3D semiconductor stack

A method and apparatus are provided for implementing an enhanced three dimensional (3D) semiconductor stack. A chip carrier has an aperture of a first length and first width. A first chip has at least one of a second length greater than the first length or a second width greater than the first width; a second chip attached to the first chip, the second chip having at least one of a third length less than the first length or a third width less than the first width; the first chip attached to the chip carrier by connections in an overlap region defined by at least one of the first and second lengths or the first and second widths; the second chip extending into the aperture; and a heat spreader attached to the chip carrier and in thermal contact with the first chip for dissipating heat from both the first chip and second chip.
Inventors:
; ;
Issue Date:
OSTI Identifier:
1473665
Assignee:
International Business Machines Corporation (Armonk, NY) OSTI
Patent Number(s):
10,068,886
Application Number:
14/699,988
Contract Number:
B601996
Resource Relation:
Patent File Date: 2015 Apr 29
Research Org:
International Business Machines Corporation, Armonk, NY (United States)
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English

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