Method and system for selecting data sampling phase for self timed interface logic
Abstract
An exemplary embodiment of the present invention is a method for transmitting data among processors over a plurality of parallel data lines and a clock signal line. A receiver processor receives both data and a clock signal from a sender processor. At the receiver processor a bit of the data is phased aligned with the transmitted clock signal. The phase aligning includes selecting a data phase from a plurality of data phases in a delay chain and then adjusting the selected data phase to compensate for a round-off error. Additional embodiments include a system and storage medium for transmitting data among processors over a plurality of parallel data lines and a clock signal line.
- Inventors:
- Issue Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1175195
- Patent Number(s):
- 6839861
- Application Number:
- 09/918,081
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- DOE Contract Number:
- W-7405-ENG-48
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Hoke, Joseph Michael, Ferraiolo, Frank D., Lo, Tin-Chee, and Yarolin, John Michael. Method and system for selecting data sampling phase for self timed interface logic. United States: N. p., 2005.
Web.
Hoke, Joseph Michael, Ferraiolo, Frank D., Lo, Tin-Chee, & Yarolin, John Michael. Method and system for selecting data sampling phase for self timed interface logic. United States.
Hoke, Joseph Michael, Ferraiolo, Frank D., Lo, Tin-Chee, and Yarolin, John Michael. Tue .
"Method and system for selecting data sampling phase for self timed interface logic". United States. https://www.osti.gov/servlets/purl/1175195.
@article{osti_1175195,
title = {Method and system for selecting data sampling phase for self timed interface logic},
author = {Hoke, Joseph Michael and Ferraiolo, Frank D. and Lo, Tin-Chee and Yarolin, John Michael},
abstractNote = {An exemplary embodiment of the present invention is a method for transmitting data among processors over a plurality of parallel data lines and a clock signal line. A receiver processor receives both data and a clock signal from a sender processor. At the receiver processor a bit of the data is phased aligned with the transmitted clock signal. The phase aligning includes selecting a data phase from a plurality of data phases in a delay chain and then adjusting the selected data phase to compensate for a round-off error. Additional embodiments include a system and storage medium for transmitting data among processors over a plurality of parallel data lines and a clock signal line.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2005},
month = {1}
}
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