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Title: Clock Controller For Ac Self-Timing Analysis Of Logic System

Abstract

A clock controller and clock generating method are provided for AC self-test timing analysis of a logic system. The controller includes latch circuitry which receives a DC input signal at a data input, and a pair of continuous out-of-phase clock signals at capture and launch clock inputs thereof. The latch circuitry outputs two overlapping pulses responsive to the DC input signal going high. The two overlapping pulses are provided to waveform shaper circuitry which produces therefrom two non-overlapping pulses at clock speed of the logic system to be tested. The two non-overlapping pulses are a single pair of clock pulses which facilitate AC self-test timing analysis of the logic system.

Inventors:
 [1];  [2]
  1. Fishkill, NY
  2. Rhinebeck, NY
Issue Date:
Research Org.:
Univ. of California (United States)
OSTI Identifier:
879697
Patent Number(s):
6738921
Application Number:
09/812321
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Classifications (CPCs):
G - PHYSICS G01 - MEASURING G01R - MEASURING ELECTRIC VARIABLES
DOE Contract Number:  
W-7405-ENG-48
Resource Type:
Patent
Country of Publication:
United States
Language:
English

Citation Formats

Lo, Tinchee, and Flanagan, John D. Clock Controller For Ac Self-Timing Analysis Of Logic System. United States: N. p., 2004. Web.
Lo, Tinchee, & Flanagan, John D. Clock Controller For Ac Self-Timing Analysis Of Logic System. United States.
Lo, Tinchee, and Flanagan, John D. Tue . "Clock Controller For Ac Self-Timing Analysis Of Logic System". United States. https://www.osti.gov/servlets/purl/879697.
@article{osti_879697,
title = {Clock Controller For Ac Self-Timing Analysis Of Logic System},
author = {Lo, Tinchee and Flanagan, John D},
abstractNote = {A clock controller and clock generating method are provided for AC self-test timing analysis of a logic system. The controller includes latch circuitry which receives a DC input signal at a data input, and a pair of continuous out-of-phase clock signals at capture and launch clock inputs thereof. The latch circuitry outputs two overlapping pulses responsive to the DC input signal going high. The two overlapping pulses are provided to waveform shaper circuitry which produces therefrom two non-overlapping pulses at clock speed of the logic system to be tested. The two non-overlapping pulses are a single pair of clock pulses which facilitate AC self-test timing analysis of the logic system.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2004},
month = {5}
}

Patent:

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