Several key issues on implementing delay line based TDCs using FPGAs
Journal Article
·
· Submitted to IEEE TRANS.NUCL.SCI.
OSTI ID:971382
Several topics in FPGA delay line based TDCs are discussed in this document. First, FPGA specific issues such as considerations on the delay line choice in different FPGA families, Wave Union Launchers, 'bubble proof' encoding logic, etc. are examined. Next, common problems for both FPGA TDCs and ASIC TDCs such as schemes of coarse time counter implementation, bin-by-bin calibration and noise issues due to single ended signals are discussed. Several resource/power saving design approaches for various processing stages are described in the document.
- Research Organization:
- Fermi National Accelerator Laboratory (FNAL), Batavia, IL
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC02-07CH11359
- OSTI ID:
- 971382
- Report Number(s):
- FERMILAB-PUB-09-608-E
- Journal Information:
- Submitted to IEEE TRANS.NUCL.SCI., Journal Name: Submitted to IEEE TRANS.NUCL.SCI.
- Country of Publication:
- United States
- Language:
- English
Similar Records
On-chop processing for the wave union TDC implemented in FPGA
Firmware-only implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA)
ADC and TDC implemented using FPGA
Conference
·
Fri May 01 00:00:00 EDT 2009
·
OSTI ID:981871
Firmware-only implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA)
Conference
·
Thu Nov 06 23:00:00 EST 2003
·
OSTI ID:817308
ADC and TDC implemented using FPGA
Conference
·
Thu Nov 01 00:00:00 EDT 2007
·
OSTI ID:920719