3-D readout-electronics packaging for high-bandwidth massively paralleled imager
- Los Alamos, NM
- Albuquerque, NM
Dense, massively parallel signal processing electronics are co-packaged behind associated sensor pixels. Microchips containing a linear or bilinear arrangement of photo-sensors, together with associated complex electronics, are integrated into a simple 3-D structure (a "mirror cube"). An array of photo-sensitive cells are disposed on a stacked CMOS chip's surface at a 45.degree. angle from light reflecting mirror surfaces formed on a neighboring CMOS chip surface. Image processing electronics are held within the stacked CMOS chip layers. Electrical connections couple each of said stacked CMOS chip layers and a distribution grid, the connections for distributing power and signals to components associated with each stacked CSMO chip layer.
- Research Organization:
- Los Alamos National Laboratory (LANL), Los Alamos, NM
- Sponsoring Organization:
- United States Department of Energy
- DOE Contract Number:
- W-7405-ENG-36
- Assignee:
- U.S. Department of Energy (Washington, DC)
- Patent Number(s):
- 7,309,878
- Application Number:
- 10/901,309
- OSTI ID:
- 921054
- Country of Publication:
- United States
- Language:
- English
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