SUMAC: A monitor and control tree for multi-FPGA systems
- Fermilab
The BTeV pixel trigger is a data acquisition system capable of finding tracks and vertices in real time in the BTeV pixel detector array. The trigger uses some 3000 processing elements (DSPs) arranged in three processing levels to handle a raw data rate of nearly 100 Gigabytes per second and bring the trigger rate down to 10 KHz. The trigger system has more than 6000 programmable elements, including Field Programmable Logic Arrays (FPGAs), microprocessors (DSPs, interface to the monitor and control tree through FPGAs), and others. Sumac (Serial Utility Monitor and Control tree) is used for configuring and monitoring of these devices. Its primary function is the downloading of FPGA bit streams, microprocessor programs, chip configurations, and test data. In addition, remote cpus and other devices can send messages and status back to the host. The Sumac system is capable of handling several thousand remote devices from a single host PC. Because it stores configuration data in local flash eeproms, it will be capable of achieving a complete system reboot in less than 1 second. The Sumac system is a tree hierarchy connected via high-speed serial links. Typically each board in the system will have a control node which accepts a single upstream serial link and fans out to as many as 32 downstream links. The downstream links can connect to FPGAs or to other control nodes for further fanout.
- Research Organization:
- Fermi National Accelerator Laboratory (FNAL), Batavia, IL
- Sponsoring Organization:
- USDOE Office of Energy Research (ER)
- DOE Contract Number:
- AC02-76CH03000
- OSTI ID:
- 9147
- Report Number(s):
- FERMILAB-Conf-99/179; ON: DE00009147
- Country of Publication:
- United States
- Language:
- English
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