MONOLITHIC ACTIVE PIXEL MATRIX WITH BINARY COUNTERS IN AN SOI PROCESS.
Conference
·
OSTI ID:909965
The design of a Prototype monolithic active pixel matrix, designed in a 0.15 {micro}m CMOS SOI Process, is presented. The process allowed connection between the electronics and the silicon volume under the layer of buried oxide (BOX). The small size vias traversing through the BOX and implantation of small p-type islands in the n-type bulk result in a monolithic imager. During the acquisition time, all pixels register individual radiation events incrementing the counters. The counting rate is up to 1 MHz per pixel. The contents of counters are shifted out during the readout phase. The designed prototype is an array of 64 x 64 pixels and the pixel size is 26 x 26 {micro}m{sup 2}.
- Research Organization:
- Brookhaven National Laboratory
- Sponsoring Organization:
- Doe - Office Of Science
- DOE Contract Number:
- AC02-98CH10886
- OSTI ID:
- 909965
- Report Number(s):
- BNL--77972-2007-CP; KA-04-04
- Country of Publication:
- United States
- Language:
- English
Similar Records
Monolithic Active Pixel Matrix with Binary Counters (MAMBO III) ASIC
Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC
Monolithic active pixel matrix with binary counters (MAMBO III) ASIC
Journal Article
·
Thu Dec 31 23:00:00 EST 2009
· PoS
·
OSTI ID:2521995
Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC
Conference
·
Mon Nov 01 00:00:00 EDT 2010
·
OSTI ID:1005026
Monolithic active pixel matrix with binary counters (MAMBO III) ASIC
Conference
·
Thu Dec 31 23:00:00 EST 2009
· PoS VERTEX2010:029,2010
·
OSTI ID:1010699