Copper electroplating process for sub-half-micron ULSI structures
- Lawrence Livermore National Lab., CA (United States)
- Intel Corp., Santa Clara, CA (United States)
We have utilized electroplating technology in a damascene process to produce low resistance copper interconnects in sub-half-micron ULSI patterns having aspect ratios of 2.4:1. The use of a pulsed-voltage plating technique allows trench filling capability without voids. Samples of 150 mm diameter were patterned and sputtered with a barrier layer, followed by a copper seed layer. Pulsed-voltage electroplating, deposited about 2 microns of copper uniformly (1 sigma < 5%) over the surface. The electroplated copper has low levels of impurities, excellent adhesion, excellent step coverage, and rates comparable to other deposition methods. We present details of the electroplating equipment, and data on the filling characteristics of the copper metallization which prevent void formation and reduce contact resistance.
- Research Organization:
- Lawrence Livermore National Lab., CA (United States)
- Sponsoring Organization:
- USDOE, Washington, DC (United States)
- DOE Contract Number:
- W-7405-ENG-48
- OSTI ID:
- 90406
- Report Number(s):
- UCRL-JC--119725; CONF-9506206--1; ON: DE95014674
- Country of Publication:
- United States
- Language:
- English
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