PEP-II Transverse Feedback Electronics Upgrade
The PEP-II B Factory at the Stanford Linear Accelerator Center (SLAC) requires an upgrade of the transverse feedback system electronics. The new electronics require 12-bit resolution and a minimum sampling rate of 238 Msps. A Field Programmable Gate Array (FPGA) is used to implement the feedback algorithm. The FPGA also contains an embedded PowerPC 405 (PPC-405) processor to run control system interface software for data retrieval, diagnostics, and system monitoring. The design of this system is based on the Xilinx{reg_sign} ML300 Development Platform, a circuit board set containing an FPGA with an embedded processor, a large memory bank, and other peripherals. This paper discusses the design of a digital feedback system based on an FPGA with an embedded processor. Discussion will include specifications, component selection, and integration with the ML300 design.
- Research Organization:
- Stanford Linear Accelerator Center (SLAC)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC02-76SF00515
- OSTI ID:
- 877439
- Report Number(s):
- SLAC-PUB-11753
- Country of Publication:
- United States
- Language:
- English
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