Cache performance in vector supercomputers

Book · Sat Dec 31 04:00:00 EST 1994

OSTI ID:87629

Kontothanassis, L I; Scott, M L ^[1]; Sugumar, R A ^[2]; Smith, J E ^[3]

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1. Univ. of Rochester, NY (United States). Computer Science Dept.
2. Cray Research Inc., Chippewa Falls, WI (United States)
3. Univ. of Wisconsin, Madison, WI (United States). Dept. of Electrical and Computer Engineering

Traditional supercomputers use a flat multi-bank SRAM memory organization to supply high bandwidth at low latency. Most other computers use a hierarchical organization with a small SRAM cache and slower, cheaper DRAM for main memory. Such systems rely heavily on data locality for achieving optimum performance. This paper evaluates cache-based memory systems for vector supercomputers. The authors develop a simulation model for a cache-based version of the Cray Research C90 and use the NAS parallel benchmarks to provide a large scale workload. They show that while catches reduce memory traffic and improve the performance of plain DRAM memory, they still lag behind cacheless SRAM. They identify the performance bottle-necks in DRAM-based memory systems and quantify their contribution to program performance degradation. They find the data fetch strategy to be a significant parameter affecting performance, evaluate the performance of several fetch policies, and show that small fetch sizes improve performance by maximizing the use of available memory bandwidth.

• OSTI ID: 87629
• Report Number(s): CONF-941118--; ISBN 0-8186-6605-6
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
COMPUTER ARCHITECTURE
CRAY COMPUTERS
EXPERIMENTAL DATA
MEMORY DEVICES
PERFORMANCE
SUPERCOMPUTERS
VECTOR PROCESSING