Small circuits for cryptography.

Technical Report · Sat Oct 01 00:00:00 EDT 2005

DOI:https://doi.org/10.2172/875977· OSTI ID:875977

Torgerson, Mark Dolan; Draelos, Timothy John; Schroeppel, Richard Crabtree; Miller, Russell D; Anderson, William Erik

This report examines a number of hardware circuit design issues associated with implementing certain functions in FPGA and ASIC technologies. Here we show circuit designs for AES and SHA-1 that have an extremely small hardware footprint, yet show reasonably good performance characteristics as compared to the state of the art designs found in the literature. Our AES performance numbers are fueled by an optimized composite field S-box design for the Stratix chipset. Our SHA-1 designs use register packing and feedback functionalities of the Stratix LE, which reduce the logic element usage by as much as 72% as compared to other SHA-1 designs.

• Research Organization: Sandia National Laboratories
• Sponsoring Organization: USDOE
• DOE Contract Number: AC04-94AL85000
• OSTI ID: 875977
• Report Number(s): SAND2005-6137
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
Cryptography.
DATA TRANSMISSION
DESIGN
ELECTRONIC CIRCUITS
Electronic circuit design
FEEDBACK
PERFORMANCE
SECRECY PROTECTION