Gated integrator with signal baseline subtraction

Patent · Mon Jan 01 04:00:00 EST 1996

OSTI ID:870742

Wang, Xucheng ^[1]

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1. Lisle, IL

An ultrafast, high precision gated integrator includes an opamp having differential inputs. A signal to be integrated is applied to one of the differential inputs through a first input network, and a signal indicative of the DC offset component of the signal to be integrated is applied to the other of the differential inputs through a second input network. A pair of electronic switches in the first and second input networks define an integrating period when they are closed. The first and second input networks are substantially symmetrically constructed of matched components so that error components introduced by the electronic switches appear symmetrically in both input circuits and, hence, are nullified by the common mode rejection of the integrating opamp. The signal indicative of the DC offset component is provided by a sample and hold circuit actuated as the integrating period begins. The symmetrical configuration of the integrating circuit improves accuracy and speed by balancing out common mode errors, by permitting the use of high speed switching elements and high speed opamps and by permitting the use of a small integrating time constant. The sample and hold circuit substantially eliminates the error caused by the input signal baseline offset during a single integrating window.

• Research Organization: Argonne National Laboratory (ANL), Argonne, IL
• DOE Contract Number: W-31109-ENG-38
• Assignee: University of Chicago (Chicago, IL)
• Patent Number(s): US 5585756
• OSTI ID: 870742
• Country of Publication: United States
• Language: English

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