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Title: Firmware-only implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA)

Abstract

A Time-to-Digital Converter (TDC) implemented in general purpose field-programmable gate array (FPGA) for the Fermilab CKM experiment will be presented. The TDC uses a delay chain and register array structure to produce lower bits in addition to higher bits from a clock counter. Lacking the direct controls custom chips, the FPGA implementation of the delay chain and register array structure had to address two major problems: (1) the logic elements used for the delay chain and register array structure must be placed and routed by the FPGA compiler in a predictable manner, to assure uniformity of the TDC binning and short-term stability. (2) The delay variation due to temperature and power supply voltage must be compensated for to assure long-term stability. They used the chain structures in the existing FPGAs that the venders designed for general purpose such as carry algorithm or logic expansion to solve the first problem. To compensate for delay variations, they studied several digital compensation strategies that can be implemented in the same FPGA device. Some bench-top test results will also be presented in this document.

Authors:
; ;
Publication Date:
Research Org.:
Fermi National Accelerator Lab., Batavia, IL (US)
Sponsoring Org.:
USDOE Office of Energy Research (ER) (US)
OSTI Identifier:
817308
Report Number(s):
FERMILAB-Conf-03/358-E
TRN: US0305166
DOE Contract Number:  
AC02-76CH03000
Resource Type:
Conference
Resource Relation:
Conference: IEEE NSS 2003, Portland, OR (US), 10/19/2003--10/25/2003; Other Information: PBD: 7 Nov 2003
Country of Publication:
United States
Language:
English
Subject:
43 PARTICLE ACCELERATORS; ALGORITHMS; AVAILABILITY; FERMILAB; IMPLEMENTATION; STABILITY

Citation Formats

Jinyuan Wu, Zonghan Shi, and Irena Y Wang. Firmware-only implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA). United States: N. p., 2003. Web.
Jinyuan Wu, Zonghan Shi, & Irena Y Wang. Firmware-only implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA). United States.
Jinyuan Wu, Zonghan Shi, and Irena Y Wang. Fri . "Firmware-only implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA)". United States. https://www.osti.gov/servlets/purl/817308.
@article{osti_817308,
title = {Firmware-only implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA)},
author = {Jinyuan Wu and Zonghan Shi and Irena Y Wang},
abstractNote = {A Time-to-Digital Converter (TDC) implemented in general purpose field-programmable gate array (FPGA) for the Fermilab CKM experiment will be presented. The TDC uses a delay chain and register array structure to produce lower bits in addition to higher bits from a clock counter. Lacking the direct controls custom chips, the FPGA implementation of the delay chain and register array structure had to address two major problems: (1) the logic elements used for the delay chain and register array structure must be placed and routed by the FPGA compiler in a predictable manner, to assure uniformity of the TDC binning and short-term stability. (2) The delay variation due to temperature and power supply voltage must be compensated for to assure long-term stability. They used the chain structures in the existing FPGAs that the venders designed for general purpose such as carry algorithm or logic expansion to solve the first problem. To compensate for delay variations, they studied several digital compensation strategies that can be implemented in the same FPGA device. Some bench-top test results will also be presented in this document.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Fri Nov 07 00:00:00 EST 2003},
month = {Fri Nov 07 00:00:00 EST 2003}
}

Conference:
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