Using LSI processor bit-slices to build a PDP-11: a case study in microcomputer design. [PDP-11 computer architecture built with bipolar microcomputer bit-slices]
Conference
·
OSTI ID:7320705
Design and evaluation are given for the CMU-11: a fully operational implementation of the PDP-11 computer architecture built with Intel 3000 Schottky bipolar microcomputer bit-slices. This project was initiated to test in detail the claims that LSI processor bit-slices simplify the design of microprogramed processors. The CMU-11 executes approximately 240,000 instructions per second, which is about 63 percent the speed of the PDP-11/40 and twice the speed of the LSI-11. The additional logic that was added to enable the Intel 3000 circuits to emulate the PDP-11 instruction set is explored in some detail. Full DEC Unibus compatibility was specified, and 29 percent of the integrated circuits used to implement the CMU-11 were required to provide buffering and control of the Unibus. The other main sources of inefficiency were the lack of arithmetic overflow logic in the bit-slices and the organization of the microinstruction control store. Improved LSI circuits in this area can substantially reduce the size (and cost) of the processor. The set of design aids currently available at Carnegie-Mellon University was of critical assistance in this project; a critique of the use of these design aids is included to show their utility in prototype design efforts. 7 figures, 8 tables.
- Research Organization:
- California Univ., Livermore (USA). Lawrence Livermore Lab.
- DOE Contract Number:
- W-7405-ENG-48
- OSTI ID:
- 7320705
- Report Number(s):
- UCRL-79581; CONF-770669-1
- Country of Publication:
- United States
- Language:
- English
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