The MAFT architecture for distributed fault tolerance
Journal Article
·
· IEEE Trans. Comput.; (United States)
This paper describes the Multicomputer Architecture for Fault-Tolerance (MAFT), a distributed system designed to provide extremely reliable computation in real-time control systems. MAFT is based on the physical and functional partitioning of executive functions from application functions. The implementation of the executive functions in a special-purpose hardware processor allows the fault-tolerance functions to be transparent to the application programs and minimizes overhead. Byzantine Agreement and Approximate Agreement algorithms are employed for critical system parameters. MAFT supports the use of multiversion hardware and software to tolerate built-in or generic faults. Graceful degradation and restoration of the application workload is permitted in response to the exclusion and readmission of nodes, respectively.
- Research Organization:
- Dept. of Computer Science, Univ. of Nebraska, Lincoln, NE (US)
- OSTI ID:
- 7245083
- Journal Information:
- IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. 37:4; ISSN ITCOB
- Country of Publication:
- United States
- Language:
- English
Similar Records
Guaranteed deadlines for hard real-time fault-tolerant distributed systems
Fault tolerance for VLSI multicomputers
SFT: Scalable Fault Tolerance
Thesis/Dissertation
·
Sat Dec 31 23:00:00 EST 1988
·
OSTI ID:6037957
Fault tolerance for VLSI multicomputers
Thesis/Dissertation
·
Mon Dec 31 23:00:00 EST 1984
·
OSTI ID:5127488
SFT: Scalable Fault Tolerance
Journal Article
·
Sat Apr 15 00:00:00 EDT 2006
· Operating Systems Review, 40(2):55 - 62
·
OSTI ID:918857