Transient reduction analysis using neural networks (TRANN)

Conference · Wed Jan 01 04:00:00 EST 1992

OSTI ID:7113111

Larson, P T; Sheaffer, D A

Our telemetry department has an application for a data categorization/compression of a high speed transient signal in a short period of time. Categorization of the signal reveals important system performance and compression is required because of the terminal nature of our telemetry testing. Until recently, the hardware for the system of this type did not exist. A new exploratory device from Intel has the capability to meet these extreme requirements. This integrated circuit is an analog neural network capable of performing 2 billion connections per second. The two main advantages of this chip over traditional hardware are the obvious computation speed of the device and the ability to compute a three layer feed-forward neural network classifier. The initial investigative development work using the Intel chip has been completed. The results from this proof of concept will show data categorization/compression performed on the neural network integrated circuit in real time. We will propose a preliminary design for a transient measurement system employing the Intel integrated circuit.

• Research Organization: Sandia National Labs., Livermore, CA (United States)
• Sponsoring Organization: DOE; USDOE, Washington, DC (United States)
• DOE Contract Number: AC04-76DR00789
• OSTI ID: 7113111
• Report Number(s): SAND-92-8494C; CONF-921065--1; ON: DE92012150
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
COMMUNICATIONS
DATA TRANSMISSION
ELECTRONIC CIRCUITS
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
NEURAL NETWORKS
PATTERN RECOGNITION
SIGNAL CONDITIONING