A new algorithm for cyclic and pipeline data conversion

Journal Article · Wed Jan 31 23:00:00 EST 1990 · IEEE Transactions on Circuits and Systems (Institute of Electrical and Electronics Engineers); (USA)

DOI:https://doi.org/10.1109/31.45717· OSTI ID:7091149

Watanabe, K; Tagami, T ^[1]; Temes, G C ^[2]

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1. Shizuoka Univ. (Japan)
2. California Univ., Los Angeles, CA (USA). Dept. of Electrical Engineering

A new algorithm is proposed for digital-to-analog conversion. The conversion starts with the most significant bit. This algorithm can be implemented using unity-gain buffers, and thus permits high-speed data conversion. Switched-capacitor D/A and A/D converter architectures based on this algorithm are described, and experimental results are presented to demonstrate its validity. Error analysis shows that a conversion accuracy of at least 9 bits is obtainable with a monolithic implementation. Computer simulations indicate that video-frequency operation may be possible if fine-line CMOS, bipolar or BiCMOS technology is used.

• OSTI ID: 7091149
• Journal Information: IEEE Transactions on Circuits and Systems (Institute of Electrical and Electronics Engineers); (USA), Journal Name: IEEE Transactions on Circuits and Systems (Institute of Electrical and Electronics Engineers); (USA) Vol. 37:2; ISSN 0098-4094; ISSN ICSYB
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ALGORITHMS
COMPUTER ARCHITECTURE
COMPUTERIZED SIMULATION
DIGITAL-TO-ANALOG CONVERTERS
ELECTRONIC EQUIPMENT
EQUIPMENT
MATHEMATICAL LOGIC
MOS TRANSISTORS
PIPELINES
SEMICONDUCTOR DEVICES
SIMULATION
TECHNOLOGY ASSESSMENT
TRANSISTORS