Advanced lift-off planarization process for Josephson integrated circuits
An advanced lift-off planarization process utilizing an undercut technique of a photoresist etching mask has been developed to achieve planarization of thin-sputtered and fine-patterned films that are necessary for high-performance Josephson integrated circuits (IC's). A stack of the same kind of photoresist layers, including the modified layer between them, has been utilized as an etching mask providing fine-patterned film profiles with minimized resist degradation by the top photoresist protection layer. This advanced planarization process brings about smooth surfaces having no residues and no grooves along pattern edges. 30 nm deviation from planarity has been demonstrated on a 200-nm-thick planarized Nb superconducting layer. A four-level interconnection of Josephson IC's was successfully fabricated by this process.
- Research Organization:
- Microelectronics Research Laboratories, NEC Corporation, 4-1-1, Miyazaki, Miyamae-ku, Kawasaki, Kanagawa 213, Japan
- OSTI ID:
- 7075592
- Journal Information:
- Appl. Phys. Lett.; (United States), Journal Name: Appl. Phys. Lett.; (United States) Vol. 53:4; ISSN APPLA
- Country of Publication:
- United States
- Language:
- English
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Method for etching thin films of niobium and niobium-containing compounds for preparing superconductive circuits
Method for etching thin films of niobium and niobium-containing compounds for preparing superconductive circuits
Related Subjects
420201* -- Engineering-- Cryogenic Equipment & Devices
420800 -- Engineering-- Electronic Circuits & Devices-- (-1989)
71 CLASSICAL AND QUANTUM MECHANICS
GENERAL PHYSICS
ELECTRONIC CIRCUITS
ETCHING
FABRICATION
FILMS
INTEGRATED CIRCUITS
JOSEPHSON JUNCTIONS
JUNCTIONS
MICROELECTRONIC CIRCUITS
PERFORMANCE
SUPERCONDUCTING JUNCTIONS
SURFACE FINISHING
THIN FILMS