Massively parallel architecture for quadratic digital filters

Journal Article · Sun Dec 31 23:00:00 EST 1989 · IEEE Transactions on Circuits and Systems (Institute of Electrical and Electronics Engineers); (USA)

DOI:https://doi.org/10.1109/31.45700· OSTI ID:7052284

Hatzinakos, D; Nikias, C ^[1]; Venetsanopoulos, A N ^[2]

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1. Dept. of Electrical and Computer Engineering, Northeastern Univ., Boston, MA (US)
2. Toronto Univ., ON (Canada). Dept. of Electrical Engineering

A massively parallel architecture for quadratic digital filters is introduced. It is obtained by using matrix and vector decomposition forms and consists of a set of parallel one-dimensional IIR filters in cascade with square-in add-out type of operations. The new architecture exhibits great modularity and regularity as well as flexibility and generality. The data throughput delay, cost that is proportional to chip area and roundoff error effects of the new structure are derived and comparisons with other already available implementations are made.

• OSTI ID: 7052284
• Journal Information: IEEE Transactions on Circuits and Systems (Institute of Electrical and Electronics Engineers); (USA), Journal Name: IEEE Transactions on Circuits and Systems (Institute of Electrical and Electronics Engineers); (USA) Journal Issue: 1 Vol. 37:1; ISSN 0098-4094; ISSN ICSYB
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
COMPUTER ARCHITECTURE
DIGITAL FILTERS
IMPLEMENTATION
MEMORY DEVICES
PARALLEL PROCESSING
PROGRAMMING