High speed processor for fastbus
Conference
·
OSTI ID:7021972
A processor designed to operate at a speed compatible with fastbus is described. It has been used in an experiment at the AGS in Brookhaven National Laboratory. Its function was to read data from various fastbus modules and store them in a buffer where they could later be read and further processed by a slower host computer. The data were formated so that the host computer could more easily process them. The processor also made decisions based on the validity of the data and rejected bad events. The ratio of the number of triggers to the number of accepted events was about 20 to 1. 3 tables.
- Research Organization:
- Yale Univ., New Haven, CT (USA); Brookhaven National Lab., Upton, NY (USA); Academia Sinica, Bejing (China)
- DOE Contract Number:
- AC02-76CH00016
- OSTI ID:
- 7021972
- Report Number(s):
- BNL-28614; CONF-801103-39
- Country of Publication:
- United States
- Language:
- English
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